View MX812_4655847.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data bulletin vsr codec with dram control preliminary information features and applications ? selectable sample rates and memory size MX812dw MX812j 28-pin soic 28-pin cdip ? half-duplex voice storage and retrieval ? serial bus m m m m m processor control ? on-chip dram controller ? up to 2 minutes of high-quality recorded audio ? answering functions and voice- notepad ? low-power 5-volt cmos figure 1 - MX812 voice store and retrieve codec clock external dram 1 or 2 x 1mbit dram chips or 1 x 4mbit dram chip serial clock command data reply data irq chip select clock generator audio in audio out v bias e bias we cas ras1 a10/r2 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d dgnd v dd v ss power meter status register mode register cv s d codec demod store/play/wait command buffer dram control mod serial c-bus interface and logic ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. MX812
vsr codec with dram control 2 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. 1 cas: this output should be connected to the column address strobe input pin(s) of all dram devices installed. 2 we: this output should be connected to the write enable input pin(s) of all dram devices installed. 3d: digital (speech) data into and out of the vsr codec. this pin should be connected to the data in and data out pins (d and q) of dram devices. 4 xtal: the nominal 4.0mhz clock input to the vsr codec. the signal applied to this device may be derived from the attached audio processor on-chip xtal oscillator circuits (see figures 2 and 3). note that the vsr codec will be able to function and maintain correct dram refresh, with xtal input frequencies down to 2.0mhz. compand and local decoder time constants will change accordingly and minimum c-bus timings (figures 6 and 7) would have to be increased pro-rata. 5 interrupt request (irq): this interrupt request output from the MX812 is wire-or able allowing the interrupt outputs of other peripherals to be commoned and connected to the interrupt input of the m processor (see the c-bus interface and system applications document). this input has a low- impedance pulldown to v ss when active, and a high-impedance when inactive. 6 serial clock: the c-bus serial clock input. this clock produced by the m controller, is used for transfer timing of commands and data to and from the vsr codec. see timing diagrams. 7 command data: the c-bus serial (command) data input from the m controller. data is loaded to this device in 8-bit bytes msb (b7) first and lsb (b0) last, synchronized to the serial clock. 8 chip select (cs): the c-bus data transfer control function. this input is provided by the m controller. transfer sequences are initiated, completed or aborted by this signal. see timing diagrams. 9 reply data: the c-bus serial data output to the m controller. the transmission of reply bytes is synchronized to the serial clock under the control of the chip select input. this is a 3-state output which is held at a high-impedance when not sending data to the m controller. 10 v bias : the output of the internal analog circuitry bias line, held internally at v dd /2. this pin should be decoupled to v ss by capacitor c 2 (see figure 2). description the MX812 is a half-duplex vsr codec, which when connected to an audio processing microcircuit (such as the mx816, 826 or 836), provides the storage and recovery of speechband audio in attached dynamic ram. the addition of this device will enhance the communications system by providing cellular radios with answering functions, message-notepad and general announcement cababilities. the MX812 will enable: ? storage of a speech message for transmission (replay) at a later time. ? storage of a received speech message when the operator is not attending. ? the storage and subsequent replay of speech. all vsr operating functions are controlled by a simple serial m processor interface which may operate from the radios own m processor/controller. pin function input audio from the store output of the audio processor is digitized by delta modulation and stored via the dram controller, in attached memory. audio for replay is recovered from the assigned memory locations and after demodulation made available for supply to the play input of the audio processor. for use with other audio systems, the input/ output audio can be connected to relevant points in circuit. the MX812 has no on-chip input or output audio filtering; this capability must therefore be provided by the host system. sampling rates and memory capacity are selectable to 32kb/s or 63kb/s and 1 x 4mbit or 2 x 1mbit respectively, which when used in conjunction allow control of audio-quality and storage-time. this low-power cmos device is available 28-pin plastic soic and 28-pin cerdip packages.
vsr codec with dram control 3 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. 11 audio out: the analog output to the audio processor play input when the vsr codec is configured as a decoder. when configured as an active decoder but with no play page commands (62 h ) active, the vsr codec will play-out an idle pattern of 101010........10 s . when not configured as a decoder, or powersaved (mode register), this output will be held at v bias via an internal 500k w resistor. the output at this pin is unfiltered; an external speechband filter C such as that included on the mx816/826/836 audio processors C will be required. since this output is centered around v dd /2 a coupling capacitor is required. 12 e bias : the encoder d.c. internal balancing circuitry line. this pin should be decoupled to v ss by capacitor c 4 (see figure 2). note that in the encode mode (mode register de and ps both 0) the codec drives this pin to approximately v dd /2 through a very high impedance; it can take more than one second for the e bias voltage to stabilize when power is first applied to this device. a faster start-up can be achieved by setting bit de or ps to 1 for 250ms (approx) during power-up. this will cause the e bias pin to be connected to v bias through a resistance of approximately 100k w . 13 audio in: the analog input to the vsr codec in the encode mode. when not configured as an encoder, or powersaved (mode register), this input will be held at v bias via an internal 500k w resistor. this pin should be coupled via a capacitor, see figure 2. as this input does not contain an internal audio filter, the audio to this pin should be limited to a 3400hz speechband by an external audio filter C such as included in the mx816/826/836 audio processors. 14 v ss : the analog ground connection. see d gnd description. 15 a0: 16 a1: 17 a2: 18 a3: 19 a4: 20 a5: 21 a6: 22 a7: 23 a8: 24 a9: 25 a10/r2: a dual function output pin selected by the memory size (ms) bit (mode register), as detailed in the table below: ms bit drams connected to this output 0 1mbits' dram no 2 ras ras2 1 4mbit dram a10 a10 signal 26 ras: an output from the vsr codec which should be connected to the row address strobe pin of the 4mbit dram or the first 1mbit dram, see figure 4, example dram connections. 27 d gnd : the digital signal ground connection to the vsr codec. both d gnd and v ss pins should be connected to the negative side of the d.c. power supply. however, a printed circuit board should be laid out so that d gnd is connected as closely as possible to the dram section ground pins. 28 v dd : positive supply rail. a single, stable +5-volt supply is required. levels and voltages within the vsr codec are dependent upon this supply. this pin should be decoupled to v ss via capacitor c 5 , located close to the MX812 pins. pin function dram address line outputs from the MX812. these pins should be connected to the corresponding address inputs of the associated dram.
vsr codec with dram control 4 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. component value c 1 dependent upon the input impedance of the driven stage c 2 1.0 m f c 3 0.1 m f c 4 1.0 m f non-electrolytic tolerance: capacitors = -50/+100% application information figure 3 - interfacing to an audio processor figure 2 - recommended external components MX812j 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d d xtal serial clock command data reply data audio out audio in a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d r a m a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 we irq cs cas a10/r2 ras v dd d gnd d gnd ras a10/r2 v dd v bias e bias v ss we cas c 1 c 3 c 2 c 4 c 5 + 5.0v cellular audio processor eg. mx8n6 v dd MX812 v ss ss xtal/clock xtal store play audio in audio out e bias v bias v bias xtal v cc v
vsr codec with dram control 5 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. application information ...... bank select dram no 1 dram no 2 inputs pages pages ab 0 C 1023 1024 C 2047 00 10 01 11 driving two 4-mbit dram sections by adding external logic circuitry, the MX812 can be configured to drive two 4-mbit dram sections. this will have the effect of doubling the available storage time. i.e. 4 minutes at 32kbps. with reference to the circuitry shown in figure 5: with the mode register ms bit set to 0 the MX812 treats the dram sections as two 1-mbit devices. the external logic makes each 4-mbit dram appear as four 1-mbit banks selected by the bank select lines a and b . figure 5 - use of external elements to drive two 4-mbit dram chips a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d we MX812 4mbit. dram v dd v ss d gnd v cc + 5.0v + 5.0v a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d cas q 1mbit. dram. no.1 v ss v cc a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d cas q v ss v cc a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d we cas ras1 a10/r2 MX812 v dd d gnd 1mbit. dram. no.2 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d w cas ras q ras ras w w we cas ras1 a10/r2 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d w cas q 4mbit dram no. 1 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d we cas a10/r2 MX812 4mbit dram no. 2 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d w cas q a b bank select inputs 'hc04 'hc00 ras ras ras1 choice of dram devices dram devices chosen should be standard 1,048,576 x 1 or 4,194,304 x 1 dynamic random access memories, with cas before ras refresh, and a row address access time of 200 nano-seconds or less. figure 4 - example dram connections
vsr codec with dram control 6 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. the controlling system: c-bus hardware interface c-bus is mx-com's proprietary standard for the transmission of commands and data between a m controller and mx-com's new generation integrated circuits. c-bus is designed for a low ic pin-count, flexibility in handling variable amounts of data, and simplicity of system design and m controller software. it may be used with any m controller, and can, if desired, take advantage of the hardware serial i/o functions built into many types of m controller. because of this flexibility and because the bus data-rate is determined solely by the m controller, the system designer can choose a m controller appropriate to the overall system processing requirements. control of the functions and levels within the MX812 vsr codec is by a group of address/commands and appended data instructions from the system m controller to set/adjust the functions and elements of the MX812. the use of these instructions is detailed in the following paragraphs and tables. command address/command (a/c) byte + data assignment hex. binary byte/s msb lsb general reset 01 0 0 0 00001 write to mode register 60 0 1 1 00000 + 1 byte instruction to mode register read status register 61 0 1 1 00001 + 1 byte reply from status register store/play page 62 0 1 1 00010 + 2 bytes command wait 63 0 1 1 00011 table 1 C c-bus address/commands write to mode register C a/c 60 h , followed by 1 byte of command data. interrupts the MX812's interrupt output is driven by the status bit 7 (if) when the mode register bit7 (ie) is set to a 1. the if bit and the interrupt output (if enabled) are set when the store/play/wait command buffer is emptied (mt bit) by transferring from the buffer to the dram control circuits. and/or the if bit and the interrupt output (if enabled) are set when a store, play or wait command has finished and the command buffer is empty. the notes below illustrate the irq pin conditions: if bit ie bit irq 0 cleared 0 disable high z 0 cleared 1 enable high z 1 interrupt 0 disable high z 1 interrupt 1 enable v ss (logic 0) general reset C a/c 01 h upon power-up the bits in the MX812 registers will be random (either 0 or 1). a general reset command (01 h ) will be required to reset all microcircuits on the c-bus, and has the following effect upon the MX812. clear all mode register bits to 0 status register bit 7 (if) to 0 bits 5 and 6 (mt and i) to 1 halt any current store, play or wait execution clear the store/play/wait command buffer interrupt output C ie controls the MX812 irq output driver. sampling rates C sr the cvsd codec sampling rates. accurate rates depend upon the applied xtal/clock frequency (see table 5). memory size C ms the MX812 can operate with 1 x 1mbit, 2 x 1mbit or 1 x 4mbit of dram (see figure 4). powersave C ps powersaves the cvsd codec only. logic functions and dram refresh are maintained. decode/encode C de the codec and dram operational mode. play or store mode bits transmitted to 812 first interrupt output enable disable sampling rate 63kb/s 32kb/s memory (dram) size single 4mbit 1 or 2 x 1mbit powersave cvsd codec powersaved cvsd codec powered decode/encode decode C play mode encode C store mode not used set to zeros setting msb 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 210 000 table 2 - control register
vsr codec with dram control 7 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. the controlling system ...... status bits received from 812 first interrupt condition (flag) bit 6 or 5 set to a 1 cleared condition command buffer buffer empty cleared condition device condition idle storing, playing or waiting input power level reading msb 7 1 0 6 1 0 5 1 0 43210 table 3 status register read status register C a/c 61 h , followed by 1 byte of reply data. interrupt condition (flag) C if set to a logic 1 whenever bit 6 or bit 5 goes from 0 to 1 (unless the transition is caused by a general reset command 01 h ). this indication allows monitoring by poll while interrupts are disabled. cleared to a logic 0 by a general reset command or immediately following a read of the status register. command buffer status C mt set to a logic 1 when the command buffer is empty or by a general reset command. cleared to a logic 0 by loading a new store, play, wait commands. device condition C i set to a logic 1 when no store, play or wait command is being executed or by a general reset command. set to a logic 0 while a store, play or wait command is being executed. encode input power level C power available in the encode mode, a 5-bit representation of the analog signal input level, updated at the end of every store or wait command. this permits the MX812 to perform a continuous sequence of store, play or wait commands, without gaps and without requiring an unduly fast response from the mcontroller. note that this command buffer can only hold one store, play or wait instruction, each new command received into this buffer will overwrite any previously loaded contents. to store or play a sequence of pages the relevant commands should be loaded with sequential page numbers while observing the status register C bit 6. store/play/wait command buffer a buffer used to accept and hold the latest store, play or wait command received over the c-bus while the MX812 is executing the previous command. the status register, bit 6, indicates the condition of this buffer. when a command is received it is first loaded into this buffer. if the MX812 is already executing a previously loaded store, play or wait command the new command will be stored temporarily in the command buffer, from where it will be taken on completion of the previous command. for the purposes of storage and replay, the attatched dram is divided into data-pages of 1024 bits (1kbit). one store/play command (loaded msb first) will instruct the MX812 to store or play (depending upon the setting of the mode register, bit-3) to or from 1 x 1024 page of dram. the store/play/wait command buffer will allow continuity of store/play page C a/c 62 h , followed by 2 bytes of command data. operation. the particular page selected is identified by the 12 lowest bits of the 2 x store/play bytes as shown below. if a store command is loaded and executed whilst the codec is powersaved in the encode mode, the selected dram page will be filled with an idle pattern (101010.....). wait C a/c 63 h , CC wait for 1024 bit periods causes the MX812 to wait for 1024 bit periods (approximately 16 or 32ms). if the codec is set to the encode mode, a new power reading that is relevant to the input audio level, will be loaded into the status register at the end of the wait period. if the codec is set to the decode mode it will play a perfect idle pattern (101010..........) during the wait period. dram size valid page nos bit nos 4mbit 0 C 4095 0 C 11 1 + 1mbit 0 C 2047 0 C 10 1mbit 0 C 1023 0 C 9 bit number msb C loaded to MX812 first loaded last C lsb bit1514131211109876543210bit value x x x x 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 value page 0 0 0 0 CCCCCCCCCCCCCCCCCCCCCCC dram page number CCCCCCCCCCCCCCCCCCCCCCC page
vsr codec with dram control 8 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. figure 8 - typical command sequences figure 7 - control timing relationships figure 6 - control timing information control timing information figure 6 shows the timing parameters for two-way communication between the m controller and cellular peripherals on the c-bus. figure 7 shows the timing relationships between the serial clock and data. chip select serial clock command data reply data address/command byte first data byte last data byte first reply data byte last reply data byte logic level is not important msb lsb 76543210 76543210 76543210 msb lsb 76543210 76543210 t t t csoff t csh hiz t nxt t nxt ck t cse t t t t t t t ch ck cdh rdh rds cds cl 70% vdd 30% vdd command data (from c) serial clock (from c) reply data (to c) i bit (idle) device condition mt bit command buffer status if bit (flag) interrupt (irq) output new 'store, play or wait' command from c-bus c1 c2 c3 read status register ** ** ** ** the value read from the status register at these times will include a valid 'power' reading if the codec is set to the encode mode. c1 c2 c3 command executing
vsr codec with dram control 9 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. control timing information ...... timing specification C figures 6 and 7 characteristics see note min. typ. max. unit t cse cs-enable to clock-high 2.0 C C s t csh last clock-high to cs-high 4.0 C C s t hiz cs-high to reply output tri-state C C 2.0 s t csoff cs-high time between transactions 2.0 C C s t ck clock-cycle time 2.0 C C s t nxt inter-byte time 4.0 C C s t ch serial clock-high period 500 C C ns t cl serial clock-low period 500 C C ns t cds command data set-up time 250 C C ns t cdh command data hold time 0 C C ns t rds reply data set-up time 250 C C ns t rdh repy data hold time 50.0 C C ns address line decoding ma0 to ma21 are the outputs of the internal 22-bit dram address counter, which are time multiplexed as row and column addresses onto the dram address lines a0 to a10 etc., as shown below. memory size (ms) bit = 1 C 4mbit dram pin a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10/r2 row address ma0 ma2 ma4 ma6 ma8 ma10 ma12 ma14 ma16 ma18 ma20 column address ma1 ma3 ma5 ma7 ma9 ma11 ma13 ma15 ma17 ma19 ma21 memory size (ms) bit = 0 C 1mbit dram(s) pin a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 row address ma0 ma2 ma4 ma6 ma8 ma10 ma12 ma14 ma16 ma18 column address ma1 ma3 ma5 ma7 ma9 ma11 ma13 ma15 ma17 ma19 ma20 ma21 ras1 a10/r2 dram selected 0 x active first 1 x active second x = don't care table 4 address line decoding sample rate (sr) bit division xtal/clock frequency (mhz) ratio 4.0 4.032 4.096 sr = 1 64 kbps 62.5 kbps 63 kbps 64 kbps sr = 0 128 kbps 31.25 kbps 31.5 kbps 32 kbps internal clock rate local decoder clock 125 khz 126 khz 128 khz table 5 sampling clock rates available
vsr codec with dram control 10 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. performance figure 10 - typical power reading vs input level plot figure 9 - typical sinad vs input level plot performance figure 9 shows a typical graph of sinad vs input level produced for both 32kbps and 63kbps sample rates at an input frequency of 1.0khz. figure 10 shows a typical graph of the power reading for increasing input signal levels. the power figure (0 to 31) is the binary figure obtained from the 5-bit representation in the status register - bits 0, 1, 2, 3 and 4 while the codec is selected to the encode mode. this reading is updated at the end of every store or wait command; excessive input signal levels will record 11111 2 (31 10 ). 0 5 10 15 20 25 30 35 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0db. (308mvrms) 6 input level (db) . 3 sinad (db) sample rate = 63kb/s sample rate = 32kb/s sample rate 63kbps sample rate 32kbps 010 20 30 1 10 100 1000 input level (mvrms) log scale 'power' reading lin scale
vsr codec with dram control 11 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. specifications absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not suggested. supply voltage -0.3 to 7.0 v input voltage at any pin (ref v ss = 0v) -0.3 to (v dd +0.3v) sink/source current (supply pins) 30ma (other pins) 20ma total device dissipation @ t amb 25c 800mw max. derating 10mw/c operating temperature -40c to +85c storage temperature -55c to +125c operating limits all devices were measured under the following conditions unless otherwise noted. v dd = 5.0v t amb = 25c xtal/clock f 0 = 4.00mhz audio level 0db ref = 308mvrms @ 1khz reply data line loaded with 50pf/200k w to v ss characteristics see note min. typ. max. unit static values supply voltage 4.5 5.0 5.5 v supply current enabled 1 C 3.0 C ma powersaved 1 C 1.0 C ma analog input impedance C 100 C k w analog output impedance (decode) C 1.0 C k w analog output impedance (encode or powersave) C 500 C k w dram interface input logic 1 2 3.5 C C v input logic 0 2 C C 1.5 v output logic 1 (at i o = -120 m a) 3 2.7 C C v output logic 0 (at i o = 120 m a) 3 C C 0.4 v input leakage current (at v in = 0 to v dd ) 4 -1.0 C 1.0 m a input capacitance 2 C 10.0 C pf digital interface input logic 1 5 3.5 C C v input logic 0 5 C C 1.5 v i in (logic 1 or 0) 5 -1.0 C 1.0 m a output logic levels output logic 1 (-120 m a) 6 4.6 C C v output logic 0 (360 m a) 7 C C 0.4 v i out tri-state (logic 1 or 0) 6 -4.0 C 4.0 m a input capacitance 5 C C 7.5 pf iox (v out = 5v) 8 C C 4.0 m a
vsr codec with dram control 12 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. dynamic values xtal pin input frequency range 12 4.0 4.1 mhz store mode analog input signal levels 9 -24.0 C 4.0 db analog input signal frequency range 9, 10 300 3400 hz recommended signal source impedance 9 C C 2.0 k w play mode analog output signal levels 13 -7.0 C -5.0 db output noise (idle) 11 C -55.0 C dbp overall store to play performance output noise (input short circuit) 11 C -50.0 C dbp sinad ( sr = 32kb/s) (input = 1.0khz @ -6.0db) 11 C 23.0 C db characteristics see note min. typ. max. unit notes 1. not including dram current. 2. d input from dram 3. outputs to dram. 4. all digital inputs. 5. serial clock, command data and chip select inputs. 6. reply data output. 7. reply data and interrupt (irq) outputs. 8. leakage current into the off interrupt (irq) output. 9. for optimum performance. 10. input filtering must be performed at the source. 11. measured in conjunction with the fx836 r2000 system audio processor. 12. for full c-bus compatibility. 13. playback of a stored -6.0db 1.0khz test signal.
vsr codec with dram control 13 MX812 preliminary information ? 1997 mx com inc. www.mxcom.com tele: 800 638-5577 910 744-5050 fax: 910 744-5054 doc. # 20480076.003 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective com panies. package outline figure 11 shows the MX812j ceramic dual in-line, or cerdip, package. the MX812dw is shown in figure 12. pin 1 is marked with an indent spot on each chip. pins number counter- clockwise when viewed from the top side. handling precautions the MX812 is a cmos lsi circuit which includes input protection. however, precautions should be taken to prevent static discharges which may cause damage. figure 11 - MX812j 28-pin cerdip figure 12 - MX812dw soic-28 package r p j k m l n a b f g e c h d pin 1 dimension in,(mm) a b c d e f g h j k l m n p r min. 0.698 (17.72) 0.291 (7.39) 0.092 (2.33) 0.004 (0.102) 0.014 (0.36) 0.050 (1.27) 0.026 (0.66) 0.096 (2.43) 5 0.020 (0.51) 0.025 (0.63) 0.041 (1.04) 0.009 (0.23) 5 0.39 (9.91) max. 0.706 (17.97) 0.299 (7.59) typical 0.012 (0.304) 0.018 (0.46) typical typical 0.104 (2.64) typical 0.040 (1.02) typical typical 0.011 (0.28) typical 0.414 (10.51) package tolerances ? ? ? ? a b ? ? ? ? ? ? ? ? ? ? ? ? ? e f g c d h dimension in,(mm) a b c d e f g h j k l min. 1.44 (36.58) 0.51 (13.06) 0.18 (4.49) 0.12 (3.0) 0.10 (2.54) 0.018 (0.45) 0.055 (1.39) 0.02 (.50) 0.61 (15.50) 0.670 (17.0) 0.009 (0.25) max. 1.46 (37.05) 0.53 (13.36) 0.220 (5.57) 0.15 (3.81) typical typical typical 0.05 (1.30) 0.62 (15.70) typical typical ? ? ? ? ? ? j k l pin 1 package tolerances
cml product data in the process of creating a more global image, the three standard product semiconductor companies of cml microsystems plc (consumer microcircuits limited (uk), mx-com, inc (usa) and cml microcircuits (singapore) pte ltd) have undergone name changes and, whilst maintaining their separate new names (cml microcircuits (uk) ltd, cml microcircuits (usa) inc and cml microcircuits (singapore) pte ltd ), now operate under the single title cml microcircuits . these companies are all 100% owned operating companies of the cml microsystems plc group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. cml microcircuits product prefix codes until the latter part of 1996, the differentiator between products manufactured and sold from mxcom, inc. and consumer microcircuits limited were denoted by the prefixes mx and fx respectively. these products use the same silicon etc. and today still carry the same prefixes. in the latter part of 1996, both companies adopted the common prefix: cmx. this notification is relevant product information to which it is attached. cml microcircuits (usa) [formerly mx-com, inc.] product textual marking on cml microcircuits (usa) products, the ?mx-com? textual logo is being replaced by a ?cml? textual logo. company contact information is as below: cml microcircuits (uk)ltd communication semiconductors cml microcircuits communication semiconductors cml microcircuits (singapore)pteltd communication semiconductors cml microcircuits (usa) inc. communication semiconductors oval park, langford, maldon, essex, cm9 6wg, england tel: +44 (0)1621 875500 fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com 4800 bethania station road, winston-salem, nc 27105, usa tel: +1 336 744 5050, 0800 638 5577 fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com no 2 kallang pudding road, 09-05/ 06 mactech industrial building, singapore 349307 tel: +65 7450426 fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com d/cml (d)/2 may 2002

▲Up To Search▲

Price & Availability of MX812

	To Download MX812 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .